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BSI
FEATURES
Very Low Power/Voltage CMOS SRAM 64K X 16 bit
DESCRIPTION
BS616LV1013
* Very low operation voltage : 2.7 ~ 3.6V * Very low power consumption : Vcc = 3.0V C-grade : 20mA (Max.) operating current I - grade : 25mA (Max.) operating current 0.02uA (Typ.) CMOS standby current High speed access time : -70 70ns (Max.) at Vcc = 3.0V * Automatic power down when chip is deselected * Three state outputs and TTL compatible * Fully static operation * Data retention supply voltage as low as 1.5V * Easy expansion with CE and OE options * I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV1013 is a high performance, very low power CMOS Static Random Access Memory organized as 65,536 words by 16 bits and operates from a wide range of 2.7V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.02uA and maximum access time of 70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable(CE) and active LOW output enable(OE) and three-state output drivers. The BS616LV1013 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV1013 is available in the JEDEC standard 44-pin TSOP Type II and 48-pin BGA package.
PRODUCT FAMILY
PRODUCT FAMILY BS616LV1013EC BS616LV1013AC BS616LV1013EI BS616LV1013AI OPERATING TEMPERATURE Vcc RANGE SPEED (ns)
Vcc=3.0V
POWER DISSIPATION STANDBY Operating
(ICCSB1, Max) (ICC, Max)
PKG TYPE TSOP2-44 BGA-48-0608
Vcc=3.0 V
Vcc=3.0 V
+0 C to +70 C
O O
O
O
2.7V ~ 3.6V
70
0.5uA
20mA
-40 C to +85 C
2.7V ~ 3.6V
70
1.5uA
25mA
TSOP2-44 BGA-48-0608
PIN CONFIGURATIONS
A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 6 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 NC
BLOCK DIAGRAM
A8 A13 A15 A14 A12 A7 A6 A5 A4
Address Input Buffer
BS616LV1013EC BS616LV1013EI
18 Row Decoder
512 Memory Array 512 x 2048
2048 DQ0 16 Data Input Buffer 16 Column I/O
2
3
4
5
A
LB
OE
A0
A1
A2
NC
. . . .
DQ15
. . . .
Write Driver
Sense Amp 128 Column Decoder
16
Data Output
16
Buffer
B
IO8
UB
A3
A4
CE
IO0
C
IO9
IO10
A5
A6
IO1
IO2
CE WE OE UB LB Control
14 Address Input Buffer
D
VSS
IO11
NC
A7
IO3
VCC
E
VCC
IO12
NC
NC
IO4
VSS
A11 A9 A3 A2 A1 A0 A10
F
IO14
IO13
A14
A15
IO5
IO6
Vcc Gnd
G
IO15
NC
A12
A13
WE
IO7
H
NC
A8
A9
A10
A11
NC
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV1013
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Revision 1.1 Jan. 2004
BSI
PIN DESCRIPTIONS
BS616LV1013
Name
A0-A15 Address Input CE Chip Enable Input
Function
These 16 address inputs select one of the 65,536 x 16-bit words in the RAM. CE is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input DQ0 - DQ15 Data Input/Output Ports Vcc Gnd
Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground
TRUTH TABLE
MODE Not selected (Power Down) Output Disabled Read CE H L L WE X H H OE X H L LB X X L H L L Write L L X H L UB X X L L H L L H DQ0~DQ7 High Z High Z Dout High Z Dout Din X Din DQ8~DQ15 High Z High Z Dout Dout High Z Din Din X Vcc CURRENT ICCSB, ICCSB1 ICC ICC ICC ICC ICC ICC ICC
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BSI
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER
Terminal Voltage Respect to GND with
BS616LV1013
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
0 C to +70 C -40 C to +85 C
O O O O
Vcc
2.7V ~ 3.6V 2.7V ~ 3.6V
Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
C C
O
W mA
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CIN CDQ
PARAMETER Input Capacitance Input/Output Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V VI/O=0V
6 8
pF pF
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER NAME
VIL VIH IIL ILO VOL VOH ICC ICCSB ICCSB1
PARAMETER
Guaranteed Input Low (2) Voltage Guaranteed Input High (2) Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL Standby Current-CMOS
TEST CONDITIONS
Vcc=3.0V
MIN. TYP.
-0.5 2.0 --Vcc=3.0V
(1)
MAX.
0.8 Vcc+0.2 1 1 0.4 -20 1
UNITS
V V uA uA V V mA mA uA
---------
Vcc=3.0V
Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 2mA Vcc = Min, IOH = -1mA CE = VIL, IDQ = 0mA, F = Fmax CE = VIH, IDQ = 0mA CE Vcc -0.2V, VIN Vcc - 0.2V or VIN 0.2V
(3)
-2.4 ----
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
0.02
0.5
1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )
SYMBOL
VDR ICCDR tCDR tR
PARAMETER
Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
25OC
TEST CONDITIONS
CE Vcc - 0.2V VIN Vcc - 0.2V or VIN 0.2V CE Vcc - 0.2V VIN Vcc - 0.2V or VIN 0.2V See Retention Waveform
MIN.
1.5 -0 TRC
(2)
TYP. (1)
-0.02 ---
MAX.
-0.3 ---
UNITS
V uA ns ns
1. Vcc = 1.5V, TA = + 2. tRC = Read Cycle Time
R0201-BS616LV1013
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Revision 1.1 Jan. 2004
BSI
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
BS616LV1013
Vcc
VIH
Vcc
VDR 1.5V
Vcc
t CDR
CE Vcc - 0.2V
tR
VIH
CE
AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 1V/ns 0.5Vcc
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L
1269
OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF "STATE
AC TEST LOADS AND WAVEFORMS
3.3V OUTPUT
100PF
INCLUDING JIG AND SCOPE
1269
3.3V OUTPUT
MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY
5PF
INCLUDING JIG AND SCOPE
,
1404
1404
FIGURE 1A
THEVENIN EQUIVALENT 667
FIGURE 1B
OUTPUT
1.73V
ALL INPUT PULSES
Vcc GND
10%
90% 90%
10%
5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC , Vcc = 3.0V )
READ CYCLE
JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Data Byte Control to Output High Z Output Disable to Output in High Z Data Hold from Address Change CYCLE TIME : 70ns MIN. TYP. MAX.
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns
t AVAX t AVQV t E1LQV t BA t GLQV t E1LQX t BE t GLQX t E1HQZ t BDO t GHQZ t AXOX
t RC t AA t ACS t BA t OE t CLZ t BE t OLZ t CHZ t BDO t OHZ t OH
70 -(CE) (LB,UB) (CE) (LB,UB) (CE) (LB,UB) ---10 10 10 ---10
-------------
-70 70 40 50 ---35 30 30 --
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BSI
SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1
(1,2,4)
BS616LV1013
t RC
ADDRESS
t
D OUT
t
OH
AA
t OH
READ CYCLE2
(1,3,4)
CE
t ACS t BA
LB,UB
t BE
D OUT
t
(5) CLZ
t BDO
t
(5)
CHZ
READ CYCLE3
(1,4)
t
RC
ADDRESS
t
OE
AA
t OE
CE
t OH
t OLZ t CLZ
(5)
t
ACS
t OHZ (5) (1,5) t CHZ t BA
LB,UB
t BE
D OUT
NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.
t BDO
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BSI
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC , Vcc = 3.0V )
WRITE CYCLE
JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION
Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time Date Byte Control to End of Write Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active
BS616LV1013
CYCLE TIME : 70ns MIN. TYP. MAX.
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns
t AVAX t E1LWH t AVWL t AVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ tWHOX
t WC t CW t AS t AW t WP t WR t BW t WHZ t DW t DH t OHZ t OW
70 70 0 70 50 (CE,WE) (LB,UB) 0 60 -30 0 -5
-------------
-------30 --30 --
SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1)
t WC
ADDRESS
t WR
OE
(3)
t CW
CE
(5)
(11)
t BW
LB,UB
t AW
WE
(3)
t AS
(4,10)
t WP
(2)
t OHZ
D OUT
t t DW
DH
D IN
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Revision 1.1 Jan. 2004
BSI
WRITE CYCLE2 (1,6)
BS616LV1013
t WC
ADDRESS
t CW
CE
(5)
(11)
t BW
LB,UB
t AW
WE
t WR t WP
(2)
(3)
t AS
(4,10)
t WHZ
D OUT
t t DW t
OW
(7)
(8)
DH
(8,9)
D IN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. 12. The change of Read/Write cycle must accompany with CE or address toggled.
R0201-BS616LV1013
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Revision 1.1 Jan. 2004
BSI
ORDERING INFORMATION
BS616LV1013
BS616LV1013 X X
Z
YY
SPEED 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE E: TSOP2-44 A: BGA-48-0608
Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.
PACKAGE DIMENSIONS
TSOP2-44
R0201-BS616LV1013
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Revision 1.1 Jan. 2004
BSI
PACKAGE DIMENSIONS (continued)
NOTES:
BS616LV1013
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75
D1
e
VIEW A
48 mini-BGA (6 x 8)
E1
R0201-BS616LV1013
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Revision 1.1 Jan. 2004

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